1. Field of the Invention
Generally, the present invention relates to the formation of integrated circuits, and, more particularly, to the formation of crystalline semiconductor regions of different characteristics, such as different charge carrier mobilities in channel regions of a field effect transistor, on a single substrate.
2. Description of the Related Art
The fabrication of integrated circuits requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout. Generally, a plurality of process technologies are currently practiced, wherein, for complex circuitry, such as microprocessors, storage chips and the like, MOS technology is currently the most promising approach due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using MOS technology, millions of transistors, i.e., N-channel transistors and/or P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A MOS transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped drain and source regions with an inversely doped channel region disposed between the drain region and the source region.
The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed above the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the charge carriers, and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, in combination with the capability of rapidly creating a conductive channel below the insulating layer upon application of the control voltage to the gate electrode, the conductivity of the channel region substantially determines the performance of MOS transistors. Thus, the reduction of the channel length, and associated therewith the reduction of the channel resistivity, renders the channel length a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
The continuing shrinkage of the transistor dimensions, however, entails a plurality of issues associated therewith that have to be addressed so as to not unduly offset the advantages obtained by steadily decreasing the channel length of MOS transistors. One major problem in this respect is the development of enhanced photolithography and etch strategies to reliably and reproducibly create circuit elements of critical dimensions, such as the gate electrode of the transistors, for a new device generation. Moreover, highly sophisticated dopant profiles, in the vertical direction as well as in the lateral direction, are required in the drain and source regions to provide low sheet and contact resistivity in combination with a desired channel controllability. In addition, the vertical location of the PN junctions with respect to the gate insulation layer also represents a critical design criterion in view of leakage current control. Hence, reducing the channel length also requires reducing the depth of the drain and source regions with respect to the interface formed by the gate insulation layer and the channel region, thereby requiring sophisticated implantation techniques. According to other approaches, epitaxially grown regions are formed with a specified offset to the gate electrode, which are referred to as raised drain and source regions, to provide increased conductivity of the raised drain and source regions, while at the same time maintaining a shallow PN junction with respect to the gate insulation layer.
Since the continuous size reduction of the critical dimensions, i.e., the gate length of the transistors, necessitates the adaptation and possibly the new development of highly complex process techniques concerning the above-identified process steps, it has been proposed to also enhance device performance of the transistor elements by increasing the charge carrier mobility in the channel region for a given channel length, thereby offering the potential for achieving a performance improvement that is comparable with the advance to a future technology node while avoiding many of the above process adaptations associated with device scaling. In principle, at least two mechanisms may be used, in combination or separately, to increase the mobility of the charge carriers in the channel region. First, the dopant concentration within the channel region may be reduced, thereby reducing scattering events for the charge carriers and thus increasing the conductivity. However, reducing the dopant concentration in the channel region significantly affects the threshold voltage of the transistor device, thereby presently making a reduction of the dopant concentration a less attractive approach unless other mechanisms are developed to adjust a desired threshold voltage. Second, the lattice structure, typically a (100) surface orientation, in the channel region may be modified, for instance by creating tensile or compressive stress to produce a corresponding strain in the channel region, which results in a modified mobility for electrons and holes, respectively. For example, creating tensile strain in the channel region increases the mobility of electrons, wherein, depending on the magnitude and direction of the tensile strain, an increase in mobility of 120% or more may be obtained, which, in turn, may directly translate into a corresponding increase in the conductivity. On the other hand, compressive strain in the channel region may increase the mobility of holes, thereby providing the potential for enhancing the performance of P-type transistors. The introduction of stress or strain engineering into integrated circuit fabrication is an extremely promising approach for further device generations, since, for example, strained silicon may be considered as a “new” type of semiconductor material, which may enable the fabrication of fast powerful semiconductor devices without requiring expensive semiconductor materials and manufacturing techniques.
Consequently, it has been proposed to introduce, for instance, a silicon/germanium layer or a silicon/carbon layer in or below the channel region to create tensile or compressive stress that may result in a corresponding strain. Although the transistor performance may be considerably enhanced by the introduction of stress-creating layers in or below the channel region, significant efforts have to be made to implement the formation of corresponding stress layers into the conventional and well-approved MOS technique. For instance, additional epitaxial growth techniques have to be developed and implemented into the process flow to form the germanium- or carbon-containing stress layers at appropriate locations in or below the channel region. Hence, process complexity is significantly increased, thereby also increasing production costs and the potential for a reduction in production yield.
Thus, in other approaches, external stress, created by, for instance, overlaying layers, spacer elements and the like, is used in an attempt to create a desired strain within the channel region. However, the process of creating the strain in the channel region by applying a specified external stress suffers from a highly inefficient translation of the external stress into strain in the channel region, since the channel region is strongly bonded to the buried insulating layer in silicon-on-insulator (SOI) devices or the remaining bulk silicon in bulk devices. Hence, although providing significant advantages over the above-discussed approach requiring additional stress layers within the channel region, the moderately low strain obtained renders the latter approach less attractive.
Recently, it has been proposed to provide so-called hybrid orientation substrates that include silicon regions of two different orientations, that is, a (100) surface orientation and a (110) surface orientation, due to the well-known fact that the hole mobility in (110) silicon along the <110> direction is maximal and is approximately 2.5 times the mobility in (100) silicon. Thus, by providing a (110) channel region for P-channel transistors in CMOS circuits, while maintaining the (100) orientation providing a superior electron mobility in the channel regions of the N-channel transistors, the performance of circuits containing both types of transistors may significantly be enhanced for any given transistor architecture, as for instance the electron mobility is maximal in a (100) plane along a <110> direction.
FIG. 1 schematically shows a cross-sectional view of a typical conventional hybrid orientation substrate that may be used for the formation of transistor elements in and on silicon regions having different orientations. In FIG. 1, a substrate 100 comprises a base substrate 101, which is comprised of crystalline silicon having a specified crystallographic orientation such as a (110) orientation. Formed in the base substrate 101 is a shallow trench isolation structure 102 comprised of insulating materials, such as silicon dioxide, silicon nitride and the like. Thus, the trench isolation structure 102 defines a crystalline region 106 having the (110) orientation and having a configuration as is typical for a silicon bulk substrate. Separated by the trench isolation structure 102 from the region 106 is a region 105 including a crystalline silicon region 103 having a different orientation, such as a (100) orientation, wherein the region 103 is bounded in the depth direction by a buried oxide layer 104. Consequently, the region 105 represents a typical SOI configuration.
The substrate 100 may be formed by well-established wafer bond techniques to form a substrate having the buried oxide layer 104 and the silicon layer 103 formed above the (110) substrate 101. Thereafter, advanced etch techniques are used to form an opening through the silicon layer 103 and the buried oxide layer 104 to expose a portion of the base substrate 101. Next, well-established selective epitaxial growth methods are employed to form a (110) silicon in the opening. After planarizing the resulting structure and forming the shallow trench isolations 102 by well-established techniques to obtain the substrate 100, transistor elements may be formed in and on the regions 106, 105 in conformity with device requirements.
Although the conventional substrate 100 provides significant advantages with respect to device performance, since, for example, P-channel transistors may be formed preferably in and on the region 106, while N-channel transistors may preferably be formed in and on the region 105, significant efforts are required to adapt and/or develop process and metrology techniques that simultaneously meet the requirements for SOI devices and bulk devices. For instance, any measurement procedures during the manufacturing process require different strategies for SOI devices, formed on the region 105, compared to bulk devices, formed on the region 106, thereby requiring a great deal of effort and production time to produce the required measurement results. In addition, process steps such as etching and rapid thermal annealing, which are used during the fabrication of transistor elements, are quite sensitive to substrate properties thereby also requiring significant efforts in adapting existing techniques and developing new process recipes when processing the hybrid substrate, thereby contributing to the overall process complexity.
In view of the above-described situation, there exists a need for an improved technique that enables providing semiconductor regions of different characteristics, such as different orientations, while eliminating or at least reducing the effects of one or more of the problems identified above.